1. Field of the Invention
The present invention generally relates to computer systems and, more specifically, to a data processing device with selective data cache architecture in a computer system.
2. Discussion of Related Art
Computer systems perform various functions with sophisticated processors at high speed. The efficiencies in the computer systems are associated with the performance of memories embedded therein. Cache memories employed in the computer systems contribute to managing program information and need to be operable at higher speeds in order to enhance overall performance of the computer systems.
Multiple kinds of cache memories have been proposed with various functional structures to improve performance in correspondence with arising needs of various and complicated functions in computer systems. These cache memories include, for example, cache memories independently assigned to instructions and data, parallel cache memories for accelerating memory access times, and different-sized cache memories with hierarchical structures. Such cache memories typically operate with processing units or execution parts to access other caches.
The trends in constructing the computer systems are rapidly going to system-on-chip (SOC) architecture in which system components, such as processors, cache memories, peripheral devices, and bus interface units, are integrated as a single chip. The SOC architecture is regarded as a small computer system. Typically SOC's have two or more built-in processors: one microprocessor controls overall operations thereof; another microprocessor is a coprocessor, e.g., DSP (digital signal processor) for managing data processing operations. The DSP carries out data multiplication and accumulation, read and write operations for one or more memories, and operations for incrementing address pointer registers.
The microprocessor and the DSP independently access cache memories separately assigned to them according to address locations of external memory data. Such a separate cache system may increase the whole cache memory capacity and the occupation area in the SOC.